Field of the Invention
The invention relates in general to a method for operating a memory device and applications thereof, and more particularly to a method for operating a non-volatile memory (NVM) memory device and applications thereof.
Description of the Related Art
An NVM which is able to continually store information even when the supply of electricity is removed from the device containing the NVM cells. Recently, the most widespread used NVMs are charge trap flash (CTF) memory devices. However, as semiconductor features shrink in size and pitch, the CTF memory devices have its physical limitation of operation, and the bit density thereof cannot be further increased.
In order to solve the problems, a memory device having multi-level cells (MLCs) or triple-level cells (TLCs) each of which can save more than one bit of data per cell is provided. Since the channel layers of the MLCs or TLCs may have grain boundary traps that may trap electrons generated by the previous operations (e.g. erase/program operation), thus undesired transient current may occur during the read operation after the previous operations due to the trapped electrons. As a result, the sensing margin of the MLCs or TLCs threshold voltage (Vt) used to identify the memory state thereof may offset, and the memory states of the MLCs or TLCs determined by the read operation may not consistent with the real memory states originally identified by the verification operation that is performed right after the previous operations.
Therefore, there is a need of providing an improved method for operating an NVM device to obviate the drawbacks encountered from the prior art.